# Hydromel: \`#lang hydromel\`

**URL:** <https://racket.discourse.group/t/hydromel-lang-hydromel/1156>\
**Category:** Languages\
**Tags:** summer-lang-party\
**Created:** [July 18, 2022, 2:00am UTC](https://racket.discourse.group/t/hydromel-lang-hydromel/1156 "2022-07-18T02:00:46Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![ben\_greenman](https://yyz2.discourse-cdn.com/free1/user_avatar/racket.discourse.group/ben_greenman/32/632_2.png) [@ben\_greenman](https://racket.discourse.group/u/ben_greenman)\
**Post date:** [July 18, 2022, 2:00am UTC](https://racket.discourse.group/t/hydromel-lang-hydromel/1156/1 "2022-07-18T02:00:46Z")

</div>

Thanks to Guillaume ([@aumouvantsillage](https://github.com/aumouvantsillage)) for [Hydromel](https://github.com/aumouvantsillage/Hydromel-lang):

> Hydromel is a hardware description language inspired by VHDL, Verilog and Clash.

More details: [https://github.com/lang-party/Summer2022/issues/4](https://github.com/lang-party/Summer2022/issues/4)

Related blog post: **[Simulating Digital Circuits in Racket](http://guillaume.baierouge.fr/2021/03/14/simulating-digital-circuits-in-racket/index.html)**  
Highly recommended!

Thanks Guillaume!

Who will enter the **[Summer `#lang` party](https://github.com/lang-party/Summer2022)** next?

Ben

* * *

Example Hydromel description of a register bank:

[https://github.com/aumouvantsillage/Hydromel-lang/blob/main/examples/register\_bank/register\_bank.mel](https://github.com/aumouvantsillage/Hydromel-lang/blob/main/examples/register_bank/register_bank.mel)

```scheme
#lang hydromel

# This Source Code Form is subject to the terms of the Mozilla Public
# License, v. 2.0. If a copy of the MPL was not distributed with this
# file, You can obtain one at https://mozilla.org/MPL/2.0/.

component register_bank(T : type, LENGTH : natural)
    port write : in bit
    port addr : in unsigned(unsigned_width(LENGTH-1))
    port d : in T
    port q : out T

    signal r : array(LENGTH, T) =
        register([0 for n in 0..LENGTH-1],
                 r <- [addr => d] when write)
    q = r[addr]
end

```