# Procesor simulation in SICP **URL:** \ **Category:** Questions & Answers\ **Tags:** question\ **Created:** [February 15, 2024, 9:14pm UTC](https://racket.discourse.group/t/procesor-simulation-in-sicp/2723 "2024-02-15T21:14:39Z")\ **Posts on this page:** 1\ **Page:** 1
**Author:** ![joskoot](https://yyz2.discourse-cdn.com/free1/user_avatar/racket.discourse.group/joskoot/32/1964_2.png) [@joskoot](https://racket.discourse.group/u/joskoot)\ **Post date:** [February 15, 2024, 9:14pm UTC](https://racket.discourse.group/t/procesor-simulation-in-sicp/2723/1 "2024-02-15T21:14:39Z")
May be I have not read all, but it seems to me that the processor simulation described in SICP does not deal with the limited size of words (in registers and memory). I hope that I am wrong, but please tell me if yes or no. Addresses and words may have different sizes. A decision must be made how to deal with transfer of data between elements of different size. Furthermore, an instruction may contain a datum smaller than the word size. When transferring it do you want sign extension? I also think a register must contain two fields for proper clocking: its input and its output. At clock-raise the input is to be entered without altering the output. At clock-drop the input is to be transferred to the output. For example ADD R0 R1 -\> R0 must clock the sum of the old outputs of R0 and R1 in R0 without being disturbed by the fact that R0 changes its output after clock-drop. But as I already wrote, may be I did not read SICP well enough. Please send me your criticism on my story. Thanks, Jos PS: I have my own processor simulator and intend to put it on github. Locally the documentation installs well, but I have to adapt some things to make it install well from github with the package installer. Of course my simulator includes an assembler.