Hydromel is a hardware description language inspired by VHDL, Verilog and Clash.
More details: https://github.com/lang-party/Summer2022/issues/4
Related blog post: Simulating Digital Circuits in Racket
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Example Hydromel description of a register bank:
#lang hydromel # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. component register_bank(T : type, LENGTH : natural) port write : in bit port addr : in unsigned(unsigned_width(LENGTH-1)) port d : in T port q : out T signal r : array(LENGTH, T) = register([0 for n in 0..LENGTH-1], r <- [addr => d] when write) q = r[addr] end